A MTJ is a key component in MRAM, spin-torque MRAM, and other spintronic devices and comprises a stack with a tunnel barrier layer such as a metal oxide formed between two magnetic layers that provides a tunneling magnetoresistance (TMR) effect. Since MTJ elements are often integrated in CMOS devices, the MTJ must be thermally stable in order to withstand annealing temperatures around 400° C. for up to several hours that are commonly applied to improve the quality of the CMOS units for semiconductor purposes.
Perpendicularly magnetized MTJs (p-MTJs) wherein the free layer (FL) and reference layer (RL) have perpendicular magnetic anisotropy (PMA) are preferred over their counterparts that employ in-plane anisotropy because a p-MTJ has an advantage in a lower writing current for the same thermal stability, and better scalability. P-MTJs are a major emerging technology for use in embedded magnetic random access memory (MRAM) applications including spin torque (STT) MRAM, and in standalone MRAM applications. STT-MRAM, which uses spin-torque for writing of memory bits, was described by C. Slonezewski in “Current driven excitation of magnetic multilayers”, J. Magn. Magn. Mater. V 159, L1-L7 (1996), and is highly competitive with existing semiconductor memory technologies such as SRAM, DRAM, and flash.
P-MTJs have a general structure where an insulating tunnel barrier is sandwiched between two magnetic layers. One of the magnetic layers is called the reference layer and has a magnetization fixed in an out-of-plane direction in the (+y) direction, for example. The second magnetic layer called the free layer has a magnetization that is also “out-of-plane”, but may be switched from a (+y) direction in a parallel or P state to a (−y) direction in an anti-parallel or AP state, or vice versa. When a current is passed through the p-MTJ in a perpendicular to plane direction, the different in resistance between the P state (Rp) and AP state (Rap) can be characterized by the equation (Rap−Rp)/Rp that is also known as DRR or the magnetoresistive (MR) ratio. It is important for p-MTJ devices to have a large DRR value since this property is directly related to the read margin for the memory bit, or the ease of differentiating between the P state (0 bit) and AP state (1 bit).
Spin-torque (STT)-MRAM based technologies are desirable for nonvolatile memory applications. However, to compete with high speed embedded SRAM technologies, p-MTJs must be fabricated into high density arrays with single bits that can be written at high speed (<100 ns) at low writing currents. To achieve the goal of low writing currents, total volume in the free layer must be reduced, which is most easily achieved by reducing the physical dimensions of the p-MTJ. However, as the physical dimensions decrease, the effect of current conductance through “edge” or sidewall regions of the p-MTJ device becomes more pronounced. P-MTJs are highly susceptible to sidewall damage, both chemical and physical, induced by etching and deposition processes, and exacerbated by the CMOS process requirement of annealing at 400° C. Accordingly, these edge regions are of particular importance as crystal structure damage from etching, encapsulation, and annealing processes may greatly affect p-MTJ properties including free layer coercivity (Hc), DRR, and resistance-area product (RA).
Typically, encapsulation with a dielectric layer is used to isolate p-MTJ devices from one another in a STT-MRAM array. The dielectric layer is deposited with a chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or reactive dc-sputtering physical vapor deposition (PVD) method that involves reactive gases, radicals, ions, or other excited species having a tendency to attack p-MTJ sidewalls and damage the magnetic layers therein. Sidewall damage leads to a reduction in device performance, substantial non-uniformity between bits that translates into an undesirable larger distribution of key metrics, and lower device yields. It is important for the encapsulation layer to form a thermodynamically stable interface with p-MTJ sidewalls to prevent oxygen diffusion through a p-MTJ sidewall during an oxide dielectric layer deposition, for example, or intermixing of the dielectric layer with one or more p-MTJ layers that also results in degradation of device performance.
Although methods are available to remove sidewall damage caused by ion bombardment, and by exposure to atmosphere during dielectric layer deposition, the methods are generally time consuming and costly. Moreover, some p-MTJ sidewall damage may be too extensive to repair. There is a need to improve the encapsulation process to prevent parallel conduction along p-MTJ sidewalls, and avoid damage to the device by depositing an encapsulation layer, which will form a thermodynamically stable interface with the p-MTJ and increase DRR.